Ou are asked to design a 4h-sic p-mosfet, which will be fabricated on the same chip with the n-mosfet of problem 1. the 4h-sic p-mosfet will be used with the device of problem 1 to build a cmos logic gate (see figure below). therefore, both devices should have the same gate oxide material, oxide thickness, and oxide charge density. since the p-mosfet requires n-type region, such region was implanted to produce doping of 1x1015 cm-3. (a) calculate vt. (b) (b) if we need saturation current idss=10 ma at vg =-5v, what will be the gate width z, if you choose l= 1 μm.
(use this information referred to as problem 1
a 4h-sic p+-n-p transistor has impurity concentrations (dopants) of 2.0x1017 and 2x1016 cm-3 in the base and collector regions, respectively. the base width wb = 0.5 mm, and the device cross-section area ar=10µm x 10µm. the bulk recombination centers/cm3 is 1.0x1015 located close to ei, and the electron and hole capture cross-sections is 2x10-15 cm2.
if the emitter-base junction is forward biased to 2.8 v and the collector-base junction is also forward biased to 2.5v, calculate, the terminal currents ie, ic, and ib.
for part (a) calculate the common emitter current gain: (i) using the equation for β and (ii) using the equation β=ic/ib. compare the two values for β and explain why they two calculations agree or do not agree.
if the device was operating in the active region with vf=2.8vand vr=-20v, calculate β. did the value of β increase, decrease or remained the same?