Consider that we have a circuit that has 17-bit inputs. We also have given a control signal which helps us erase some bits from the input data. If the control signal is Logical 1, the last 5 bits are erased (equal to Logical 0) and for the Logical 0 control signal, the first 7 bits are erased. Write down the behavioral level Verilog HDL code for this circuit.

Afoot bridge is made as a simple deck, 4 m long, with a cross section 2 m (wide) and 20 cm thick, and made of wood. the deck is supported at the two ends. the maximum load allowable on the bridge is 10 tons, provided it is uniformly distributed on the deck. to sense this load, a strain gauge is placed at the center of the bridge and its resistance is monitored. if the sensor has a nominal resistance of 350 s2 and a gauge factor of 3.6, what is the reading of the strain gauge at maximum load? the modulus of elasticity for the wood used in the construction is 10 gpa.