Design a VHDL module Inputs: din, clock, reset
Output dout

The first D-Flip-Flop (DFF) should have its D input connected to a module input and the last DFF should have its Q output connected to the module output. Include a clock and a reset to the module. The reset should asynchronously reset all four DFFs. Use a separate process for each DFF

An open feedwater heater operates at steady state with liquid entering at inlet 1 with t? = 40°c and pl = 1 .2 mpa. water vapor att2-200°c and p2 = 1.2 mpa enters at inlet 2. saturated liquid water exits with a pressure of pa 1.2 mpa. neglect heat transfer with the surroundings and all kinetic and potential energy effects, determine the mass flow rate of steam at inlet 2 if the mass flow rate of liquid water at inlet 1 is given as 2 kg/s.