Construct the D-flip-flop with positive-edge triggering and asynchronous Clear. Implement the Master-Slave design with two gated D-latches from problem 2 as building blocks and inverters. The circuit inputs are D, CLOCK, CLEAR_bar; the circuit output is Q. a) Show the schematic using D-latches as building blocks and inverters. b) For your schematic estimate the propagation delays from D to Q with CLOCK =01 and from CLEAR_bar=10 to Q0. Assume a 5 ns delay for the inverter.