Design a 3-bit synchronous counter using D flip-flops. The counter will count when the enable (EN) is zero and hold when enable is one. The counter has an output, Z, which is high when the count is 100.

Explanation:

The 3-bit Synchronous binary up counter comprises of, three T flip-flops & one 2-input AND gate. All these flip-flops are negative edge triggered and the outputs of flip-flops change affect synchronously. The T inputs of first, second and third flip-flops are 1, Q0 & Q1Q0 respectively.

Please refer to attachment for the detailed image if the 3-bit synchronous counter using D flip-flops. The counter will count when the enable (EN) is zero and hold when enable is one. The counter has an output, Z, which is high when the count is 100.