Assume a simple circuit requires 2,000 mos transistors on a die and that all transistors are minimum sized. if the transistors are fabricated in a 10nm cmos process (the dimensions of a minimum-sized transistor are 10nm x 10nm) and the spacing overhead for the transistors is a factor of 10 (spacing overhcad is needcd to allow for clectrical separation between devices. with a spacing overhead of 10, often designated as 10x, the average area per transistor is assumed to be 10 times larger than the transistor itself), determine the number of die that can be fabricated on a 12" silicon wafer. neglect the area required for the bonding pads of the circuit (bonding pad area actually dominates the die area for integrated circuits with a small number of small mos transistors but is neglected in this problem)