Design a 4-bit synchronous up/down counter using combinational logic and dffs resettable to zero, with inputs: clk, reset, and inc/dec, and output: count(3: 0), such that upon reset count = "", count++ = count- – „1‟ when inc/dec = „0‟, and count = count- + „1‟ when inc/dec = „1‟. when inc/dec = „1‟ and count- = "", count+ = ""; and when inc/dec = „0‟ and count- = "", count+ = "".

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