Cache block size (b) can affect both miss rate and miss latency. assuming a machine with a base cpi of 1, and an average of 1.35 references (both instruction and data) per instruction, find the block size that minimizes the total miss latency given the ollowing miss rates for various block sizes.

8: 4% 16: 3% 32: 2% 63: 1.5% 128: 1%
a.) what is the optimal block size for a miss latency of 20 × b cycles?

b.) what is the optimal block size for a miss latency of 24 + b cycles?

c.) for constant miss latency, wha
t is the optimal block size?

Determine the time of the day and month of the year at which the peak sensible cooling load occurs for a top floor, north-eastern corner room of an office building in durban for the following conditions: floor area: 8 x 8 x 3 m east and north walls: 115 mm face brick (outside), 20 mm air space, 115 mm ordinary brick (inside) with 15 mm plaster roof construction: suspended plasterboard ceiling, 450 mm air space, 150 mm concrete, 75mm screed, waterproofing no heat transfer across other surfaces window area 3x 1,5 m high in north wall only. ordinary glass with venetian blinds. lights and occupants : from 07: 00 to 18: 00 average light density: 25 w/m2 number of occupants : 5 seated, light office work room temperature 24°c