Acomputer system designed and built in the 1970’s made use of a single 8-bit cpu-to-memory data bus and a single separate address bus. suppose that such a system contained 4 memory modules or chips, each of which was 8 bits wide with a depth of 16777216. a memory access for each module consisted of only two phases: an addressing phase in which an address is sent to select a specific memory module and cell within the module; and a data transfer phase in which the selected data item is read from or written into. each phase takes 40 nano-seconds to complete. what is the minimum time (in nano-seconds) required to read a single 32-bit data item from this memory system if it employs: a) high order interleavingb) low order interleaving