Please answer the following question in Verilog. To test our functions we will generate a 3-bit vector that counts up by one every cycle which we will use as the inputs to the decoder. The decoder output will then be fed into the inputs of the encoder to produce an inverted version of the original 3-bit test vector. For every input vector you should toggle the enable signal to both the encoder and decoder function which can be easily done by using the clock waveform used to determine when to increment the input vector as the enable signal as well.