Given the following sequence of assembly language instructions for a CPU with multiple pipelines, indicate by type (below each heading) all the data hazards that exist between instructions. i1: Add R3, R2, R1
i2: Add R4, R0, R0
i3: Add R0, R1, R2
i4: Add R3, R0, R1 ; R1
(a) Indicate all data dependencies (RAW, WAR, WAW) that exist between instructions by writing the instruction pairs among which the dependency exist.
(b) Now assume there is a data forwarding circuit in this pipelined processor and data is written in the first half-cycle and read in the second half-cycle, insert nop instructions to eliminate the data hazard in the above program. Show a pipeline execution diagram for the program, where all data forwards are marked with arrows. Moreover, on the data path circuit, identify the data value, inputs and outputs of the data forwarding unit in cycles when data is forwarded.
(c) Now assume there is a data forwarding circuit and hazard detection unit in this pipelined processor and data is written in the first half-cycle and read in the second half-cycle. Show a pipeline execution diagram for the program, where all stalls are marked with "**" and identify the inputs and outputs of the data hazard detection unit in cycles when stalls are inserted.