Let's say that an AES-128 key was 00 00 00 01 00 00 00 02 00 00 00 03 00 00 00 04. (It's a bad key because it's not random, but we'll use it in this problem anyway.) This is used as "round key 0" what are the first four bytes in "round key 1"? Write each using exactly two hex digits (using lower-case hex for a-f)

Show that there is a language a ⚆ {0, 1} â— with the following properties: 1. for all x â a, |x| ≤ 5. 2. no dfa with fewer than 9 states recognizes a. hint: you don’t have to define a explicitly; just show that it has to exist. count the number of languages satisfying (1) and the number of dfas satisfying (2), and argue that there aren’t enough dfas to recognize all those languages. to count the number of languages satisfying (1), think about writing down all the strings of length at most 5, and then to define such a language, you have to make a binary decision for each string about whether to include it in the language or not. how many ways are there to make these choices? to count the number of dfas satisfying (2), consider that a dfa behaves identically even if you rename all the states, so you can assume without loss of generality that any dfa with k states has the state set {q1, q2, . . , qk}. now think about how to count how many ways there are to choose the other four parts of the dfa.

Asequential circuit contains a register of four flip-flops. initially a binary number n (0000 ≤ n ≤ 1100) is stored in the flip-flops. after a single clock pulse is applied to the circuit, the register should contain n + 0011. in other words, the function of the sequential circuit is to add 3 to the contents of a 4-bit register. design and implement this circuit using j-k flip-flops.

You need to design a circuit that implements the functions in the following table: s0 s1 function0 0 a + 10 1 a – b1 0 a + b1 1 a – 1s0 and s1 are 1-bit control inputs to select the function of the circuit. inputs a and b are 4-bitnumbers in 2s complement form. the output is also a 4-bit number in 2s complement form.you are allowed to use only one ttl 7483 4-bit adder to implement all the functions. but anynumber of other components (except the adder) can be used.hint: design a combinational logic circuit to modify the input b and the “carry input” of theadder depending on the control inputs s0 and s1.important: lab grade will depend on the working of the circuit & will be checked of by your labinstructor.1. is the output valid for the following input combinations: a. s0 = 0, s1 = 0, a = 7, b = 3? b. s0 = 0, s1 = 1, a = 7, b = 3? c. s0 = 1, s1 = 0, a = -4, b = -5? d. s0 = 1, s1 = 1, a = -8, b = 6? 2. what is the range of inputs (for both a and b) that will produce the valid output for all the functions?