Suppose the processor has separate instruction and data caches. The miss rate for instruction cache is 5% and that for data cache is 20%. The miss penalty is 60 cycles for both caches. When there is a cache miss, the pipeline stalls, waiting for the data/instruction to be fetched from the main memory. What is the CPI overhead due to memory accesses

Pthe price of tickets in a group when a purchased in bulk can be found with the equation c=px+24 were c is the cost, p is the number of people,and x is the price per ticket. what is price of of each ticket if it costs $189 to buy tickets for 15 people ? a $8 b $24c $9d $11 show work

15: 28read the summary of "an indian's view of indian affairs."15 betterin "an indian's view of indian affairs," it is asserted that conflicts could be reduced if white americansunderstood native americans..pswhich of the following would make this summary more complete? eleo the fact that chief joseph believes the great spirit sees everythinthe fact that chief joseph was born in oregon and is thirty-eight years oldo the fact that chief joseph states that he speaks from the hearthehehethe fact that chief joseph of the nez percé tribe made this claimebell- ==feetle===-felsefe ==submitmark this and retum.=

22. sata3 allows for data transfer rates of 600 mb/s. explain why you would likely not be able to copy data from one hard drive to another at anywhere close to this speed. also, what could be upgraded on the computer to achieve transfer speeds closer to 600 mb/s