We want to compare the latency and the cycle time of a pipelined and nonpipelined processor design. Assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB
250ps 350ps 150ps 300ps 200ps

Required:
a. What is the clock cycle time in a pipelined and non-pipelined processor?
b. What is ld instruction latency in a pipelined and non-pipelined processor?
c. Assume 10 consecutive instructions are executed in the pipelined and the nonpipelined processors. What is the total execution time on the two processors?