Acircuit contains three resistors connected in parallel. the value of r1 is 2 k , the value or r2 is 6 k , and the value of r3 is 10 k . if the supplied voltage is 100 vdc, what is the total power in the circuit?

a. 2.18 w

b. 8.18 w

c. 7.67 w

d. 4.24 w

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Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?

Consider a byte-addressable computer with 16mb of main memory, a cache capable of storing a total of 64kb of data and block size of 32 bytes. (a) how many bits in the memory address? (b) how many blocks are in the cache? (c) specify the format of the memory address, including names and sizes, when the cache is: 1. direct-mapped 2. 4-way set associative 3. fully associative