Suppose you have a machine with separate I-and D-caches. The miss rate on the I-cache is 1.6%, and on the D-cache 5.4%. On an I-cache hit, the value can be read in the same cycle the data is requested. On a D-cache hit, one additional cycle is required to read the value. The miss penalty is 110 cycles for datacache, 120 for I-cache. 25% of the instructions on this RISC machine are LW or SW instructions, the only instructions that access data memory. A cycle is 1ns. What is the average memory access time