Consider two different implementation of the same instruction set architecture. The instruction can be divided into four classes according to their CPI (class A, B, C and D). P1 with clock rate of 2.5 GHz and CPIs of 1, 4, 3 and 2, and P2 with a clock 3 GHz and CPIs of 2, 3, 2 and 3. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 20% class A, 30% class B, 20% class C and 30% class D, which implementation is faster