For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache Tag Index Offset
63–10 9–5 4–0

Required:
a. What is the cache block size (in words)?
b. How many blocks does the cache have?
c. What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded.

a) 32 words

b) 32 blocks

c)   374 / 10240

Explanation:

A) Cache block size

The offset bits from given data ; = 5 bits

therefore the cache block size = 2^5 = 32 words

B) determine the number of blocks the cache have

index bits = 5 bits

therefore the number of blocks the cache have = 2^5 = 32 blocks are mapped in the cache

C ) Determine the ratio between Total bits required for such a cache implementation over the data storage  bits

 lets assume

size of each word = w

size of each word ( w ) = 32 * 10 = 320

then we have to determine the total bits = 54 + 320 = 374

also total data bits = 32 * w  = 10240

finally ratio of Total bits over data storage bits

= Total bits / total data bits

=  374 / 10240

where is the graph? post the graph then ill come back and