A. Suppose a CPU with a write-through, write-allocate cache achieves a CPI of 2. What are the read and write bandwidths (measured by bytes per cycle) between RAM and the cache? b. For a write-back, write allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a CPI of 2?

Data Reads per 1000 instructions Data Writes per 1000 instructions Instruction Cahce Miss Rate Data Cache Miss Rate Block size (Bytes)
250 100 0.30% 2% 64

Following are the solution to the given question:

Explanation:

In point 1:

I = number of program code completed.  

In such a block of the system memory, the number of iterations to read would be 64/W, while W is the length of its band.

Miss penalty (cycling):

Miss penalty is written for the data cache:

Miss penalty for the cache instruction:

The ,  Hit time + miss penalty Hit time:

In point 2:

Miss penalty read data cache:

Miss penalty for the data cache:  

Read the penalty for miss:

Total runtime = time hit + penalty mismatch