Consider a processor with a 2 ns clock cycle, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access time (hit time) of 1 clock cycle. Assume that the read and write miss penalties are the same. a. Find the average memory access time (AMAT).
b. Suppose we can improve the miss rate to 0.03 misses per instruction by doubling the cache size. However, this causes the cache access time to increase to 1.2 cycles. Using the AMAT as a metric, determine if this is a good trade-off.
c. If the cache access time determines the processor’s clock cycle time, which is often the case, AMAT may not correctly indicate whether one cache organization is better than another. If the processor’s clock cycle time must be changed to match that of a cache, is this a good tradeoff?

Assume that the processors in part (a) and (b) are identical, except for the clock rate and the cache miss rate. Assume 1.5 references per instruction (for both I-cache and D-cache) and a CPI without cache misses of 2. The miss penalty is 20 cycles for both processors.

a) 4 ns

b) 3.6 ns

Explanation:

Given that

Miss penalty = 20 * 2

Miss rate = 0.05

Clock cycle = 2 ns

Hit time = 1 * 2

The Average Memory Access Time or AMAT is found by using this formula

AMAT = Hit time + Miss rate × Miss penalty

Substituting directly for the values, we get

AMAT = 2 + [0.05 * (20 * 2 ns)]

AMAT = 2 + (0.05 * 40)

AMAT = 2 + 2

AMAT = 4 ns

b) given that

Miss rate = 0.03

Hit time = 1.2 * 2

Miss penalty remains the same = 40

AMAT = (1.2 * 2) ns + [0.03 * 40] ns

AMAT = 2.4 ns + 1.2 ns

AMAT = 3.6 ns

Considering that the AMAT is 3.6, we can say that it is a good trade-off.

c) CPU time = Clock cycle * IC * (CPIideal-cache + cache stall cycles per instruction)

CPU time

(a) = 2 ns * IC * (2 + 1.5 * 20 * 0.05) =

CPU time = 2 * IC * (2 + 1.5)

CPU time = 2 * IC * 3.5

CPU time = 7 * IC

(b)

CPU time = 2.4 ns * IC * (2 + 1.5 * 20 * 0.03)

CPU time = 2.4 * IC * (2 + 0.9)

CPU time = 2.4 * IC * 2.9

CPU time = 6.96 * IC

The CPU times we calculated in parts (a) and (b) are nearly the same. Thus, we can conclude that, doubling the cache size to improve the miss rate at the expense of stretching the clock cycle results in virtually no net gain.

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