Use the Texas Instrument website to look up the 74ALS74A DFF. *How long can it take for the Q output of a 74ALS74A to switch from 0 to 1 in response to an active CLK transition? *How long does the D input need to be stable before the active clock edge on the 74ALS74A? What is the narrowest pulse that can be applied to the PRE of a 74ALS74A FF? Use the Texas Instrument website to look up the 74ALS112A DFF. How long does it typically take to asynchronously clear a 74ALS112? How long maximum does it take to asynchronously set a 74ALS112? What is the shortest acceptable interval between active clock transitions for a 74ALS74A? The J input of a 74ALS112A goes HIGH 15 ns before the active clock edge. The K input has been at 0. Will the flip-flop be reliably set? How long does it take (after the clock edge) to synchronously store a 1 in a cleared 74ALS74A D flip-flop?