The classic five-stage pipeline MIPS architecture is used to execute the code fragments in this problem. Assume the followings The architecture fully supports forwarding, Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle, Branches are resolved in the third stage of the pipeline and the architecture does not utilize any branch prediction mechanism, Register R4 is initially 100.
1w R2, 200(R5)
add R3, R1, R2
sw R3, O(R5)
add R3, R3, R6
sw R3, 400(R5)
addi R4, R4, -4
addi R5, R5,4
brie R4, RO, Ll
a. What is the size of the memory needed to store he program? Code size: bytes
b. How many iterations are performed to complete the entire loop? Number of iterations: iterations
c. How, many nstrucfions are executed to complete the entire loop? Number of instructions executed: instructions
d. How many references are made to the data memory for read in one iteration of the loop?
e. How many references are made to the data memory for write in one iteration of the loop? Number of data references for write: references
f. How many references are made to the instruction memory in one iteration of the loop? Number of instruction memory references: references