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Design the 4-bit synchronous down-counter with enable using the counters in problem 4 as building blocks and any multiplexers. When enabled with input E=1, outputs Q3, Q2, Q1, Q0 follow the sequence from 1111 to 0000 counting down in a binary order and repeat. Otherwise with E=0 counting is disabled (no changes of state variables). Obtain the schematic.

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