Given a Fully Associative cache with 4 lines using LRU replacement. The word size is one byte, there is one word per block, and the main memory capacity is 16 bytes. Suppose the cache is initially empty and then the following addresses are accessed in the order listed: {3,4,3,7,7,12,4,8,3,12,7,9}.

3 bits

Explanation:

Capacity of main memory=16 Bytes=24

The number of address bits= 4 bits.

The size of the word= 1 Byte=20

The word bits=0.

Number of lines =4

Number of sets required=21

The sets bits is =1

The number of offset bits=20=0

Number of tag bits= total number of address bits - (word bits + offset bits + set bits)

= 4 - 0 -0- 1

= 3 bits

go ahead give the other guy a brain list he deserves it

explanation: