Computers and Technology, 10.04.2020 19:00 megancrader11

Consider the following MIPS code segment that is executed on a 5-stage pipeline architecture that does not implement forwarding or stalling in hardware. (1) add $4, $1, $1 (2) add $7, $4, $9 (3) lw $2, 40($8) (4) sub $8, $1, $2 (5) sw $8, 80($2) (6) sub $2, $8, $4 (7) lw $8, 2($1) (8) add $8, $4, $2 a. [6 marks] Identify the data dependences that cause hazards. You are to use the following format to inform each dependency reported: instruction (y) depends on instruction (z) caused by register $ b. [8 marks] If the hazards identified in (a.) are to be prevented by the compiler through no-op insertions but without reordering the instructions, indicate where would the compiler add no-ops. You are to use the following format to inform each dependency reported: insert x no-ops between instructions (y) and (z). c. [6 marks] Now assume a more intelligent compiler that can move instructions in the code. Can such a compiler reduce the number of added no-ops?

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Consider the following MIPS code segment that is executed on a 5-stage pipeline architecture that do...

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