Assume that a memory operation requires 4 nsec from the time a memory address value is available until one can assume a stable output value is available and that the maximum time for an address output delay from a rising edge (TAD) and the minimum data setup time prior to the falling edge of a clock pulse (TDS) are both 1/2 nsec. If a system designer wanted to be able to carry out consecutive memory operations without the need for wait states, what is the fastest clock speed (in MHz) that can support this.