Caches are commonly implemented in SRAM, and the cache layout impacts the total amount of SRAM required to implement the cache. For the following two problems, assume the caches are byte addressable and addresses and data words are both 32 bits. a. How many total bits are required to implement a 128 KiB direct-mapped cache with 4-word blocks? b. How many total bits are required to implement a 128 KiB direct-mapped cache with 32-word blocks?

1. ask the user how many questions are in the quiz. 2. ask the user to enter the key (that is, the correct answers). there should be one answer for each question in the quiz, and each answer should be an integer. e.g., 34 7 13 100 81 3 9 10 321 12 might be the key for a 10-question quiz. you will need to store the key in an array. 3. ask the user to enter the answers for the quiz to be graded. there needs to be one answer for each question. note that these answers do not need to be stored; each answer can simply be compared to the key as it is entered. 4. when the user has entered all of the answers to be graded, print the number correct and the percent correct. 5. add a loop so that the user can grade any number of quizzes with a single key. after the results have been printed for each quiz, ask "grade another quiz? (y/n)." note: you only have one array (the key). you are not creating a new key for each set of quiz answers.