Chegg (5 points) how many bits must each pipeline register hold? a. 32 b. enough to control all the parts of the datapath in the next stage of the pipeline. c. enough to control all the parts of the datapath in the next stage of the pipeline plus enough to control further stages in the pipeline, such as the destination register number. d. enough to hold the result of the alu operation in the previous stage of the pipeline. e. enough to hold the opcode and register numbers of the instruction being executed.