Assume a gpu architecture that contains 10 simd processors. each simd instruction is 32 bits, and each simd processor contains 8 lanes for single precision arithmetic, and load/store instructions, meaning that each non-diverged simd instruction can produce 32 results every 4 cycles. assume a kernel that has divergent branches that causes, on average 80% of threads to be active. also assume that 70% of all instructions are sp arithmetic and 20% load/store. because not all memory latencies are covered, assume an average simd instruction issue rate of 0.85. assume the gpu has a clock speed of 1.5 ghz. compute the throughput, in gflop/sec, for this code on this gpu.