Write a vhdl using 2 processes and one hot encoding to design a simple computer bus can only do bus reading. when the input read_bus is low the bus is in the state idle but when it is high the bus reads three words a, b, c in this order, each one takes one clock cycle to be performed. during the reading if read_bus drops to 0 the system does not interrupt the reading (does not come back to the idle state). after reading c, if read_bus is 0 then the system goes to state idle, but if the read_bus is equal to 1 the bus performs the reading again in the same order (a, b, then c) without coming back to the state idle.