Write a behavior model for calculating the next pc for an instruction. it will use information from the processor control module and the alu to determine the destination for the next pc. use the following module interface: module nextpclogic(nextpc, currentpc, signextimm64, branch, aluzero, uncondbranch); input [63: 0] currentpc, signextimm64; input branch, aluzero, uncondbranch; output [63: 0] nextpc; /* write your code here */endmodulewhere signextimm64 is the output of the sign extender. branch is true if the current instruction is a conditional branch instruction, uncondbranch is true if the current instruction is an unconditional branch (b), and aluzero is the zero output of the alu. any additions with a constant should have a delay of 1, general addition should have a delay of 2, and any multiplexers should have a delay of 1 (this includes statements inside if/else statements).write a test module to test your module’s correct operation. in your test code, use the $display command to print the inputs (currentpc, signextimm64, branch, aluzero, uncondbranch) and the output (nextpc).here is the testbench for the verilog code to write`timescale 1ns / 1ps`define strlen 32module nextpclogictest; task passtest; input [63: 0] actualout, expectedout; input [`strlen*8: 0] testtype; inout [7: 0] passed; if(actualout == expectedout) begin $display ("%s passed", testtype); passed = passed + 1; endelse $display ("%s failed: %d should be %d", testtype, actualout, expectedout); endtasktask allpassed; input [7: 0] passed; input [7: 0] numtests; if(passed == numtests) $display ("all tests passed"); else $display("some tests failed"); endtask// inputsreg [63: 0] currentpc, signextimm64; reg branch, aluzero, uncondbranch; reg [7: 0] passed; reg [7: 0] numtests; // outputswire [63: 0] nextpc; reg[63: 0] expectednextpc; // instantiate the unit under test (uut)nextpclogic uut(.currentpcnextpc)); initial begin// initialize inputscurrentpc = 64'b0; signextimm64 = 64'b0; branch = 1'b0; aluzero = 1'b0; uncondbranch = 1'b0; passed = 7'b0; numtests = 7'b0; #3; currentpc = 64'h10; signextimm64 = 64'b0; branch = 1'b0; aluzero = 1'b0; uncondbranch = 1'b0; expectednextpc = 64'h14; #4; passtest(nextpc, expectednextpc, "pc+4 test", passed); numtests = numtests + 1; currentpc = 64'h10; signextimm64 = 64'h2; branch = 1'b1; aluzero = 1'b1; uncondbranch = 1'b0; expectednextpc = 64'h18; #4; passtest(nextpc, expectednextpc, "conditional - take branch test", passed); numtests = numtests + 1; currentpc = 64'h10; signextimm64 = 64'h3; branch = 1'b1; aluzero = 1'b0; uncondbranch = 1'b0; expectednextpc = 64'h14; #4; passtest(nextpc, expectednextpc, "conditional - don't take branch test", passed); numtests = numtests + 1; currentpc = 64'h10; signextimm64 = 64'h4; branch = 1'b0; aluzero = 1'b0; uncondbranch = 1'b1; expectednextpc = 64'h20; #4; passtest(nextpc, expectednextpc, "unconditional branch test", passed); numtests = numtests + 1; allpassed(passed, numtests); $finish; end endmodule