This task is to implement an encoder whose input is a one 4-bit hex signal and the outputs are seven 1- bit signals for each display segment (a-g). 1. create the encoder. vhd file: a. under ""flow navigator"" click ""add sources."" b. select ""create or add design sources."" c. create task3.vhd and then click ""finish."" d. create an input named ""hex_in"" which is 4 bits wide (use a std_logic_vector for this). e. create 7 outputs named ""a"" through ""g"" which are 1 bit wide each.