Adelay between the time an address arrives in a bus to when the memory is ready to return the data is known as latency.

Column Access Strobe (CAS) latency

Explanation:

Column Access Strobe (CAS) latency is the time limit between the READ command and the  time when information is accessible.

The interval is defined in nanoseconds in  asynchronous DRAM(Dynamic random-access memory).The interval is defined in clock  cycles in synchronous DRAM.

Since latency depends on a number of clock ticks rather than absolute time, if the clock rate differs, the actual time for a SDRAM  (Synchronous dynamic random-access memory) module to respond to a CAS event may vary.

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